As the performance of an information processing device, such as a device for communication base and a server, improves, the data rate of transmission and reception of signals inside and outside such a device is increasing. In a receiving circuit of such a transmission and reception device, there are a synchronous receiving circuit that samples input data in synchronization with the phase of the input data, and an asynchronous receiving circuit that samples input data without synchronizing with the phase of the input data. The asynchronous receiving circuit generates receive data from the sampled data by interpolation.
There has been known a technique that samples a data signal whenever a constant amount of phase is shifted, and selects data on the most desirable phase (see Japanese Laid-Open Patent Publication No. 11-68727). There has been known a technique that measures a cycle which receives a special mark from transmitted data with the special mark, and that delays a sampling clock based on the cycle (see Japanese Laid-Open Patent Publication No. 2004-229068). There has been known a technique that delays a sampling clock, and uses multiphase sampling clocks in which phases are different from each other (see Japanese National Publication of International Patent Application No. 2008-526073).